Functional Verification Engineer

Project Role : Functional Verification Engineer Project Role Description : Develop and execute testbenches to verify the functional correctness of digital designs at the block and system level. Create constrained-random, directed, and coverage-driven tests using languages like SystemVerilog and UVM. Collaborate with design and architecture teams to identify corner cases and ensure complete functional coverage before tape-out. Must have skills : SoC Verification Good to have skills : NA Minimum 3 year(s) of experience is required Educational Qualification : 15 years full time education Summary: As a Functional Verification Engineer, a typical day involves designing and implementing comprehensive test environments to validate the functionality of digital hardware components. This role requires close collaboration with cross-functional teams to identify potential edge cases and ensure thorough verification coverage. The engineer actively develops various test scenarios, executes simulations, and analyzes results to confirm design integrity before final production stages. Continuous refinement of verification strategies and proactive communication with design and architecture teams are integral parts of the daily workflow, ensuring high-quality deliverables and adherence to project timelines. Roles & Responsibilities: - Expected to perform independently and become an SME. - Required active participation/contribution in team discussions. - Contribute in providing solutions to work related problems. - Collaborate effectively with design and architecture teams to enhance verification processes. - Document verification plans, test cases, and results to maintain clear communication and traceability. - Assist junior team members by sharing knowledge and providing guidance on verification methodologies. - Continuously improve verification environments and methodologies to increase efficiency and coverage. Professional & Technical Skills: - Must To Have Skills: Proficiency in SoC Verification. - Experience with SystemVerilog and Universal Verification Methodology for creating testbenches and test cases. - Strong understanding of constrained-random and coverage-driven verification techniques. - Ability to develop directed tests and analyze simulation results to identify design issues. - Familiarity with digital design concepts and hardware description languages. - Skilled in collaborating with cross-functional teams to ensure comprehensive verification coverage. Additional Information: - The candidate should have minimum 3 years of experience in SoC Verification. - This position is based at our BDC6F - SEZ location. - A 15 years full time education is required. 15 years full time education Important Notice We have been alerted to the existence of fraudulent messages asking job seekers to set up payment to cover various costs associated with establishing employment at Accenture. No one is ever required to pay for employment at Accenture. If you are contacted by someone asking for payment, please do not respond, and contact us at india.fc.check@accenture.com immediately. Equal Employment Opportunity Statement All employment decisions shall be made without regard to age, race, creed, color, religion, sex, national origin, ancestry, disability status, veteran status, sexual orientation, gender identity or expression, genetic information, marital status, citizenship status or any other basis as protected by federal, state, or local law. Please read Accenture’s Recruiting and Hiring Statement for more information on how we process your data during the Recruiting and Hiring process.